Boot procedure
nileswan uses a two-stage boot loader.
flowchart LR
C[Console IPL] -->|FPGA core 0| A0[IPL0]
A0 -->|SPI flash| A1[IPL1 /boot/]
A0 -->|SPI flash - button held| A5[IPL1 /factory/]
A0 -->|SPI flash - X3 + B held| A3[IPL1 /safe/]
A3 -->|SPI flash| A4[Recovery]
A1 -->|FPGA core 1| A2[MENU.WS /on TF card/]
A5 -->|FPGA core 0| A2[MENU.WS /on TF card/]
The first-stage boot loader is 512 bytes in size. It is stored in the factory FPGA core.
Its goal is to:
- reset the nileswan hardware,
- store the console register and I/O port state in console internal RAM,
- load IPL1 from SPI flash to console internal RAM.
The second-stage boot loader is up to 0x37C0 (14272) bytes in size. It is stored in the SPI flash. It uses a special 16-byte header:
| Offset | Size | Description |
|---|---|---|
| 0x0 | 2 | Load address (typically 0x0040) |
| 0x2 | 2 | Number of 512-byte sectors to load from SPI flash |
| 0x4 | 12 | Reserved |
It has two variants:
The “boot” variant is bundled with the storage card driver. Its goal is to:
- validate the IPC memory area and populate it if necessary,
- switch to the update-provided FPGA core (unless the factory version of IPL1 is forced by holding the on-cartridge button),
- load
/NILESWAN/MENU.WSfrom the storage card.
The “factory” variant is a version of the “boot” variant which does not load the updated firmware version’s FPGA core, allowing booting the system in the case of a corrupt firmware update.
The “safe” variant instead reserves space for testing functionality, such as:
- performing a test of onboard PSRAM and SRAM memory,
- allowing to load a dedicated recovery program from SPI flash.
The recovery program is up to 256 KiB in size (or 192 KiB for the factory-provided version). It is formatted like a standard WS cartridge image.
It is better documented as part of the User Guide.
The menu program is loaded to the final banks of PSRAM (bank 0xFF downwards). It is formatted like a standard WS cartridge image.