I/O port map

0xE0 - SPI_CNT (16-bit, read/write)

• In read mode all output serial bits are 1. The incoming bits are stored in the RX buffer.
• In write mode bits from the TX buffer are output. The incoming serial bits are discarded.
• In exchange mode the TX buffer is output, while simultaneously the RX buffer is populated with incoming data.
• Wait and read mode behaves like read mode except bytes are only stored with the first byte received which is not 0xFF.

During transfer the data in the TX buffer currently not mapped into the address space is sent out. The received data is stored in the RX buffer currently not memory mapped. The transfer always starts from the beginning of the buffers.

All values besides the transfer abort are read only while a transfer is in progress.

Transfer aborting is not immediate for internal reasons and to allow the transfer to end cleanly on a byte boundary. After an abort is issued the busy bit will continue to be high until the abort is finally completed.

For EEPROM or RTC SPI communication to work, the cartridge serial clock has to be selected.

0xE2 - POW_CNT (8-bit, read/write)

If 0xDD is written to POW_CNT it will reset the entire register even if nileswan registers are disabled. This allows unlocking the nileswan I/O ports after they have been disabled.

Disabling a range of I/O registers only changes their visibility; it does not disable their functiion. E.g. the upper banking bits of the 2003 mapper continue to apply even if the registers used to change them are not accessible anymore.

The μC reset line bit is connected directly to the nRST pin of the microcontroller.

μC BOOT0 controls whether the microcontroller starts from bootloader ROM or programmable flash (see STM32 documentation). The line is shared with busy line for emulated EEPROM operations and is open drain idling at low.

If SRAM is enabled SRAM (banks 0-7) may be selected when accessing the RAM area.

0xE3 - EMU_CNT (8-bit, read/write)

See section on EEPROM for details on EEPROM size.

When flash emulation the FPGA will provide minimal emulation of the programming sequences of parallel NOR flash memory for PSRAM accesses.

When 32 KB SRAM mirroring is enabled address line 15 of the SRAM is kept low, hence accesses to the upper 32 KB of each SRAM page are access the first 32 KB. Together with BANK_MASK it can be configured as if the cartridge contains a 32 KB SRAM.

0xE6 - BOARD_REVISION (8-bit, read)

Used for distinguishing boards during firmware updates.

0xE6 - WARMBOOT_CNT (8-bit, write)

After writing the FPGA will load one of four FPGA cores from SPI flash depending on the value written. The core image locations are documented in the SPI flash layout.

It may only be written while not running code from the cartridge. After writing, a wait of approximately 20 milliseconds is necessary until the cartridge responds again.

Important

If your FPGA core image does not enable a faster frequency range, the wait may need to be as high as 53 milliseconds.

0xE8 - IRQ_ENABLE (8-bit, read/write)

0xE9 - IRQ_STATUS (8-bit, read/write)

0xE4 - BANK_MASK (16-bit, read/write)

To allow booting from bootrom the masks are initialised with all bits set.

Bank mask is always applied to the extended ROM bank (starting from 0x40000).